Device ID

    Vendor ID

    Subsystem ID

    Subsystem Vendor ID

    Connector ID / Present

    Module ID

Using these registers the host can detect the module presence, determine if this is consistent with system requirements and respond accordingly by configuring the system or reporting system deficiencies.

The user is free to read and write to any of the Cyclic Data Buffers independent of their type (Tx or Rx). However, the Cyclic Data Buffer data transfer system only responds in strict accordance to the channel type. That is, it will transfer data, written to a Tx Cyclic Data Buffer, to the appropriate module channel and write received data to the corresponding Rx Cyclic Data Buffer.

The Cyclic Data Buffers are controlled according to simple rules. The buffer read and write pointers can be read by the host to assist in the data transfer process.

In practice, the user writes data for transmission to consecutive long word locations in the Cyclic Data Buffer. Only valid words are transmitted.

Receive data is automatically written to consecutive word locations in the cyclic data buffer.

PCI interrupts can be generated for both DMA and Module events. Interrupt Control and status registers are provided for enabling interrupts and determining which events occur.

The PMC module has been designed to be compatible with Sycos PCI card range. Consequently, interrupts respond in a hierarchical manner, according to which block of eight channels caused the interrupt. The channel which caused the interrupt can then be determined by reading a status register.

For example, in a PMC module that has 8Tx,8Rx, this is equivalent to two blocks of 4Tx,4Rx (block 0 and block 1). If an interrupt is desired when data is first detected on receive channel 0 of block 1, the PCI Interrupt Control is programmed to generate an interrupt from block 1. A local interrupt status register assigned to block 1 can then be read to determine which channel of block 1 caused the interrupt.

Separate user manuals are provided for each module. Modules have a minimum of 8 channels and maximum of 32 channels that can be used for either transmission or reception of data. Modules may also have registers and memory accessible to the user. Access to this register and memory address space is relatively slow compared with that of the Cyclic Buffers and is therefore only intended for configuration and control purposes.

Data written to a Transmit Cyclic-Data-Buffer is automatically transferred to the corresponding transmitter in a manner which ensures the maximum usage of the ARINC-429 data bus. That is, while data is available,  ARINC-429 data is transmitted with the minimum 4-bit gap between data words.

Similarly, received data can be captured at this maximum data rate and automatically transferred to the corresponding Cyclic-Data-Buffer from where it can be easily transferred over the PCI interface to the host processor.

For modules with blocks of 4Tx,4Rx the individual transmitter outputs can be looped-back on to the corresponding receive channel. When a channel is configured in this way its transmit driver outputs are disabled to prevent the test signals being received by other equipment on the ARINC-429 data bus.

PCI interrupts can be triggered immediately following reception of complete ARINC-429 data words. The interrupts are controlled and handled in a hierarchical manner so that the reception of ARINC-429 data generates a module interrupt on the mother card which generates a PCI interrupt to the host computer

Mechanical Description:

The PMC module mechanical design conforms to Common Mezzanine Card Standard P1386 [1].

The design allows for up to 32 channels of ARINC-429 interfacing to be provided on a single width PMC module, with Input/Output via a 68 pin SCSI connector on the front of the module.

A Conduction Cooled version will be available in the 4^th Quarter of 2003, whose specification is based upon VITA 20-199x/D1.9. This product will support either 8 or 16 channels of ARINC-429.