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Home > ARINC 629 Products > PCIe Products > Transmitter & Bus Monitor

Data Sheet

ARINC 629 PCIe Basic Protocol Tx and Bus Monitor Product

Sales Ref: Sy629PCIe-BPM


- Single Lane PCIe

- Embedded PCI Local Bus

- PCI interrupts on  Module Events

- Short PCIe card

- Uses Boeing approved DATAC device

- Direct access to XPP and RPP from PCIe

- Block & Independent Modes

- Choice of:

         - Dual Data Buffers or  

         - Cyclic Data Buffers


- High Resolution System Timer

- Auto Cyclic Redundancy Checking (CRC)

- Auto Refresh Counter Support

- Bus Monitoring

- Transmit Monitoring

- Error Status Reporting

- Rx Time-Stamping

- External Timer Clock input

- FIFO buffers for Rx data and Time-Stamp

- Time-Stamp resolution 0.5µS

The Sy629PCIe-BPM card provides a convenient means for transmitting and receiving data over an ARINC 629 bus in accordance with the transmit and receive programme defined by data written into the XPP and RPP memory.


The use of the recognised DATAC chip ensures full compliance with ARINC 629 specification with Basic Protocol (BP).


ARINC-629 Input/Output is via a 9-way D-Type socket on the PCIe card faceplate. All other I/O are accessible from a 25-way D-Type socket on the rear of the card.


PCIe is essentially transparent to the user and the card appears as a PCI interface to the host. This ensures compatibility with Sycos PMC and PCI solutions.


The card provides configuration registers which allow the host to:


- Automatically identify the module and its revision status.

- Assign address space for the module’s data buffer memory and registers. (Plug-in and Play).

- Control and monitor the PCI bus interface to the module.

- Read module interrupt configuration as assigned by the POST software as it initialises and configures the system.


Additional features designed into the module are:


- 16 Independent Cyclic-Data-Buffers, each with a capacity for 4k x 32-bit words.

- Direct access to the Cyclic-Data-Buffer Read / Write Pointers.

- High resolution time-stamping of received data.

- PCI interrupts on Module Events.

- Direct access to Module registers and application memory.

- Interface compatible with 32bit PCI Local bus Specification, revision 2.1, June 1995.


The PCIe module is designed to be used in a "Plug-in and Play" environment which is made possible, not only by the choice of PCIe interface, but also by the provision of various identification and module present registers. These include:


- Device ID

- Vendor ID

- Subsystem ID

- Subsystem Vendor ID

- Module ID


Using these registers the host can detect the presence of the module, determine if this is consistent with system requirements and respond accordingly by configuring the system or reporting system deficiencies.